1. Field of the Invention
Embodiments of the present invention relates to a liquid crystal display (LCD) device, and more particularly, to a gate drive circuit for an LCD device. Embodiments of the present invention are suitable for a wide scope of applications. In particular, an embodiment of the present invention is suitable for providing a gate drive circuit with a reduced defect rate, a method of repairing the gate drive circuit, and an LCD device using the gate drive circuit.
2. Description of the Related Art
Recently, gate in panel (GIP) type LCD devices have been gaining in interest because they are relatively light and thin. In a GIP LCD, a gate drive circuit is embedded in an LCD panel. This structure allows the GIP LCD to be fabricated at a reduced manufacturing cost.
FIG. 1 is a schematic description of an LCD device in accordance with the related art. Referring to FIG. 1, the related art GIP-type LCD device includes an LCD panel 3, a gate drive circuit 2 and a data drive circuit 1. The LCD panel 3 includes a plurality of gate lines G1 to Gn and a plurality of data lines D1 to Dm crossing each other. The LCD panel 3 is formed by putting a liquid crystal material between a lower array substrate and an upper array substrate to provide a liquid crystal cell Clc at each crossing of the gate lines G1 to Gn and the data lines D1 to Dm.
A thin film transistor TFT is formed at each crossing of the gate lines G1 to Gn and the data lines D1 to Dm to drive the corresponding liquid crystal cell Clc. The gate drive circuit 2 sequentially supplies a scan pulse to the gate lines G1 to Gn. The data drive circuit 1 supplies a data voltage to the data lines D1 to Dm of the LCD panel 13. The TFT supplies the data voltage from the data lines D1 to Dn to the liquid crystal cell Clc in response to the scan pulse from the gate lines G1 to Gn. For example, a gate electrode of the TFT is connected to one of the gate lines G1 to Gn, a source electrode of the TFT is connected to one of the data lines D1 to Dm, and a drain electrode of the TFT is connected to a pixel electrode of the liquid crystal cell Clc.
The gate drive circuit 2 is formed on the lower array substrate for sequentially shifting a start signal at each horizontal period to generate the scan pulse to be sequentially supplied to the gate lines G1 to Gn. A black matrix, a color filter and a common electrode (not shown) are formed on the upper array substrate of the LCD panel 3. Polarizers having their optical axes crossing each other at a right angle are placed onto the upper and lower array substrates of the LCD panel 3, respectively. An alignment film is formed on the inner surface of one or more of the lower and upper array substrate for setting a pre-tilt angle of the liquid crystal material. A storage capacitor Cst is formed in each of the liquid crystal cells Clc of the LCD panel 3. The storage capacitor Cst is formed between the pre-stage gate line and a pixel electrode of the liquid crystal cell Clc or between a common electrode line (not shown) and the pixel electrode of the liquid crystal cell Clc to fixedly keep the voltage of the liquid crystal cell Clc.
The data drive circuit 1 includes a plurality of data drive IC's. Each of the data drive IC's includes a gate drive circuit, a latch, a digital-analog converter, and an output buffer. The data drive IC may be attached to the lower array substrate of the LCD panel 3 using a tape carrier package (TCP). The data drive IC may also be directly mounted on the lower array substrate of the LCD panel 3 by a chip-on-glass method. The data drive circuit 1 latches digital video data and converts the digital video data into an analog gamma compensation voltage to be supplied to the data lines D1 to Dm.
FIG. 2 is a schematic description of the gate drive circuit of FIG. 1 in accordance with the related art. Referring to FIG. 2, the gate drive circuit 2 includes an n-number of stages S1 to Sn connected in cascade. The first to nth stages S1 to Sn respectively includes input lines LI1 to LIn connected to start input terminals TI1 to TIn and output lines LO1 to LOn connected to output terminals TO1 to TOn, and shifts the start signal inputted through the input lines LI1 to LIn to the output lines LO1 to LOn. Each of the input lines LI2 to LIn of the second to nth stages S2 to Sn is connected to a previous one of the output lines LO1 to Lon−1 of a corresponding previous one of the stages S1 to Sn−1. For example, the second input line LI2 from stage S2 is connected to the first output line LO1 from stage S1, the third input line LI3 from stage S3 is connected to the second output line LO2 from stage S2, and so on.
As shown in FIG. 2, a start pulse Vst is inputted to the first stage S1 of the gate drive circuit 2 as a start signal for the first stage S1. Each of the pre-stage output signal LO1 to Lon−1 from each of the first to (n−1)th stages is inputted to the corresponding next stage from the second to nth stages S2 to Sn as the start signal for the corresponding next stage. Each of the stages S1 to Sn may have a similar circuit configuration and shifts the start pulse Vst or the corresponding pre-stage output signal LO1 to LOn−1 in response to a clock signal CLK to generate a scan pulse having a pulse width of one horizontal period.
FIG. 3 illustrates possible drive defects on a display screen of the related art LCD panel of FIG. 1. As shown in FIG. 3, when one of the stages S1 to Sn malfunctions because of impurities, a pattern defect, etc, i.e., the kth stage which supplies the scan pulse to the kth gate line among the first to nth gate lines G1 to Gn may operate abnormally. The abnormal operation of the kth stage causes a defective driving of the kth horizontal line 7 on a display screen 5 of the LCD panel as shown in part (a) of FIG. 3. The defective driving may extend to all the area below the kth horizontal line 7 on the display screen 5 of the LCD panel as shown in part (b) of FIG. 3.
Thus, in the related art GIP LCD panel, a defective gate drive circuit affects the entire LCD panel, thereby increasing manufacturing cost. To reduce the impact of defective LCD panels on manufacturing cost, there is need to provide a gate drive circuit with a reduced defect rate. The impact on the manufacturing cost can also be reduced by providing a method of repairing the gate drive circuit.